DK-DEV-2AGX260N【PDF 34/48 页】KIT DEV FPGA 2AGX260 W/6.375G TX

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6–14

Chapter 6: Board Test System

Using the Board Test System

The HSMC Tab

The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B

ports. Figure 6–7 shows the HSMC tab.

Figure 6–7. The HSMC Tab

1

You must have the loopback HSMC installed on the HSMC connector that you are

testing for this test to work correctly.

The following sections describe the controls on the HSMC tab.

Status

The Status control displays the following status information during the loopback test:

■

■

■

PLL lock —Shows the PLL locked or unlocked state.

Channel lock —Shows the channel locked or unlocked state. When locked, all

lanes are word aligned and channel bonded.

Pattern sync —Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected.

Arria II GX FPGA Development Kit, 6G Edition User Guide

July 2010 Altera Corporation

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